Semiconductor devices, especially silicon devices, have been more highly integrated to achieve lower power consumption through miniaturization following the scaling law known as “Moore's Law”. Highly integrated devices have been developed so far at the pace of increasing the number of transistors in the devices four times every three years. In recent years, the gate length of a MOSFET is 20 nm or smaller. Because of rising costs for lithography processes, including costs of apparatus and mask set, and the physical limits such as operation limit and fluctuation limit of device scaling, there has been need for improvement in device performance through an approach other than the following scaling law.
As a functional element which is formed inside a multi-layered copper interconnect on a semiconductor device, a variable resistance type non-volatile element (hereinafter, referred to as “resistance changing element”), a capacitor (capacitance element) or the like is exemplified.
As the capacitor which is mounted on a logic LSI with other components, the embedded DRAM, the decoupling capacitor or the like is exemplified. By mounting the capacitor on a copper wiring, it is possible to make the capacitor have a large capacity and a small size.
As a device which is assessed as a middle position between the gate array and the standard cell, a device which is called as FPGA has been developed. The device makes it possible to configure desired circuit by a customer after a chip is fabricated. By intervening a resistance variable element or the like as programmable element in a wiring connection point, it becomes possible to carry out electrical wiring connection by the customer his-self. By using the semiconductor device mentioned above, it is possible to improve flexibility of a circuit design.
As the resistance changing element, ReRAM (Resistive Random Access Memory) using metal oxide, a solid electrolyte switch element using a solid electrolyte or the like is exemplified.
The resistance changing element has three layers structure that a variable resistance layer is interposed between an upper electrode and a lower electrode, and uses a phenomenon that electric resistance of the variable resistance layer is varied by applying a voltage between the electrodes. The phenomenon that the electric resistance of the variable resistance layer is varied by applying the voltage has been researched since the 1950s to the 1960s, and the phenomena that the electric resistance of a variable resistance layer 3, which use various metal oxides, is varied have been reported up to now. For example, non-patent literatures 1 and 2 report the resistance changing element which uses nickel oxide (NiO) (non-patent literatures 1 and 2).
Several researches on the solid electrolyte switch element, which uses the solid electrolyte as the variable resistance layer, have been reported since the late 1990s, and the phenomena that the electric resistance of the variable resistance layers, which are made of various solid electrolyte materials, is varied is confirmed. For example, non-patent literatures 3 and 4 report the phenomenon that the electric resistance of the variable resistance layer, which is made of the chalcogenide compound, is varied (non-patent literatures 3 and 4). Moreover, also a method for forming the element in the multi-layered copper interconnect arranged on the semiconductor device is known. For example, patent literature 1 and non-patent literature 5 report a solid electrolyte switch element which is fabricated inside a multi-layered copper interconnection layer on a CMOS substrate (patent literature 1 and non-patent literature 5).
The solid electrolyte switch element is an element which has structure that a solid electrolyte is interposed between two electrodes. For example, in the case of applying a negative voltage to one out of the two electrodes, a metal atom, which is included in the other electrode, is ionized to be eluted into the solid electrolyte, and then a metallic bridge is formed. By the metallic bridge connecting two electrodes, the switch is changed to be in an ON state which has low electric resistance. On the other hand, in the case of applying a positive voltage to one out of the two electrodes, the metallic bridge is solved into the solid electrolyte and two electrodes are electrically isolated each other. As a result, the switch is changed to be in an OFF state which has high electric resistance. As mentioned above, the solid electrolyte switch element can carry out non-volatile and repetitive switching between the ON state and the OFF state. By using the properties, it is possible to realize application to a non-volatile memory or a non-volatile switch.
Here, recently, it is required to make the semiconductor device furthermore large-scale-integrated and micronized. In order to restrain increase of wiring resistance, and capacitance between wirings which is caused by micronization, Cu/low permittivity (low-k) wiring layer is used. It is preferable to make a process temperature in a multi-layered interconnect forming process as low as possible in order to arrange each kind of BEOL (Back End Of Line) device (for example, a solid electrolyte switch element or the like) in the wiring layer. However, due to making the process temperature low, poisoning gas is evolved increasingly through a via hole, which is opened on an upper electrode of the BEOL device, in the via first dual damascene process, and a chemically amplification type material, which is included in an applied photo resist (PR), becomes inactive at a time of exposure for wiring after opening the via hole. As a result, there is a problem that a resolution failure of wiring pattern is caused.
Meanwhile, as a method for preventing the poisoning phenomenon, the multilayer resist process have been used usually. For example, the method of inserting a Spin-on-Glass (SOG) layer or an SiO2 layer as a block layer against the poisoning gas is known. As the conventional dual damascene wiring groove exposure technology, the patterning method, which uses a multilayer resist structure such as Spin-on-Carbon (SOC)/SOG/anti-reflection film (BARC: Bottom Anti Reflection Coating)/PR, SOC/SiO2/BARC/PR or the like superposed in this order from the substrate side, is known. However, since it has been progressed to make the resist thin in order to form furthermore micronized wiring pattern, and it becomes necessary to make the block layer (SOG or SiO2) thin together with to make the process temperature low. As a result, it becomes difficult to suppress the evolution of the poisoning gas thoroughly.
Moreover, a case of using the SiO2 layer as the block layer is more superior in the block properties than a case of using the SOG layer as the block layer. However, in the case of using the SiO2 layer, there is a problem that adhesiveness between the SOC layer and the SiO2 layer is weak, and consequently exfoliation is apt to be caused.
Furthermore, in the case that mis-alignment is generated, a method that only an upper resist layer (resist layer which exists over block layer) is exfoliated and removed by use of the O2 ashing or the organic solvent, and an upper resist layer is applied again, and an exposure and development process is carried out is used. However, the block film such as the SOG film or the SiO2 film, which is formed at low temperature, has a problem that its refraction factor is changed due to the O2 ashing process, and the block film is exfoliated by using the organic solvent.
Meanwhile, as another method for solving the resolution failure of wiring pattern, the method of making places, at which the poisoning gas is evolved, distributed by increasing number of the via holes per an unit area, or the method of making an etch stopping layer, which exists at a bottom of the via, have two layers structure is known. However, when forming the BEOL device inside the multi-layered copper interconnect, it is necessary to design wiring layer structure with offering preference to device properties. Then, it is desired to take a measure for solving the evolution of the poisoning gas not-dependently on the wiring layer structure.
As a method for preventing degradation of the block layer, which is caused by the above-mentioned O2 ashing, and washing by use of the organic solvent, in three-layered resist structure, a patent literature 2 discloses an art that a TEOS layer whose film is formed with the low temperature CVD method is used as the block layer (patent literature 2).
Moreover, a patent literature 3 discloses an art that, in order to improve a dry etching selectivity between an SOC layer and a block layer which is an upper layer of the SOC layer, an SiO2 layer or an Si3N4 layer whose film is formed with the CVD method using the high density plasma is used as the block layer (patent literature 3).